High voltage semiconductor component

ABSTRACT

A semiconductor component for switching high currents. The semiconductor component includes an LIGBT arrangement having island-shaped p-wells and specially designed cathode regions for improving the latch-up strength of the semiconductor component.

FIELD OF THE INVENTION

The present invention relates to a field-controlled semiconductorcomponent.

BACKGROUND INFORMATION

In German Published Patent Application No. 39 42 640 is discussed asemiconductor component in which the latch-up strength of the componentis limited by elevated hole current densities occurring at the cornersof the p-well islands.

SUMMARY OF THE INVENTION

The semiconductor component according to an exemplary embodiment of thepresent invention has the advantage that high current densities can beswitched even at high operating temperatures without latching oraffecting adjacent integrated circuit arrangements (e.g., logiccircuits). This is advantageous in particular when switching a currentfor ignition applications by a semiconductor component designed as a MOScomponent, where inductive loads are to be driven. The componentaccording to an exemplary embodiment of the present invention thepresent invention also has a high breakdown voltage of several 100 V inthe static off state as well as good on-state behavior, i.e., a voltagedrop of only a few volts in the static on state and a current density onthe order of approx. 100 A/cm² of component surface area. Furthermore,the component has a high pulse strength, i.e., it can handle a highvoltage and a high current density at the same time. A specialembodiment of cathode regions directly adjacent to an anode region hasproven to be especially advantageous.

An arrangement of interruptions in the cathode region at its corners hasproven especially advantageous.

Furthermore, a division of channel regions into two groups controlledvia separate gates is also advantageous. This is advantageous inparticular for internal voltage limiting (clamping).

In comparison with insulation with buried oxide layers, insulation ofthe component in the chip by p-walls arranged at the edge of thecomponent permits inexpensive integration of severalconductivity-modulated output stages having a high blocking ability(semiconductor components of the exemplary embodiments of to the presentinvention) or logic circuits on the same chip.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a semiconductor component.

FIG. 1a shows a view of a p-well of the semiconductor component of FIG.1.

FIG. 2 shows a view of a semiconductor component having a gateelectrode.

FIG. 3a shows another embodiment of a p-well.

FIG. 3b shows another embodiment of a p-well.

FIG. 3c shows another embodiment of a p-well.

FIG. 3d shows another embodiment of a p-well.

FIG. 3e shows another embodiment of a p-well.

FIG. 3f shows another embodiment of a p-well.

FIG. 3g shows another embodiment of a p-well.

FIG. 3h shows another embodiment of a p-well.

FIG. 3i shows another embodiment of a p-well.

FIG. 3j shows another embodiment of a p-well.

FIG. 3k shows another embodiment of a p-well.

FIG. 3l shows another embodiment of a p-well.

FIG. 3m shows another embodiment of a p-well.

FIG. 3n shows another embodiment of a p-well.

FIG. 3o shows another embodiment of a p-well.

FIG. 3p shows another embodiment of a p-well.

FIG. 3q shows another embodiment of a p-well.

FIG. 3r shows another embodiment of a p-well.

FIG. 3s shows another embodiment of a p-well.

FIG. 3t shows another embodiment of a p-well.

FIG. 3u shows another embodiment of a p-well.

FIG. 3v shows another embodiment of a p-well.

FIG. 3w shows another embodiment of a p-well.

FIG. 3x shows another embodiment of a p-well.

FIG. 3y shows another embodiment of a p-well.

FIG. 3z shows another embodiment of a p-well.

FIG. 3za shows another embodiment of a p-well.

FIG. 3zb shows another embodiment of a p-well.

FIG. 3zc shows another embodiment of a p-well.

FIG. 3zd shows another embodiment of a p-well.

FIG. 4 shows a semiconductor component having two separate gateelectrodes.

FIG. 5a shows a clamping circuit and a control circuit.

FIG. 5b shows another clamping circuit and control circuit.

FIG. 5c shows another clamping circuit and control circuit.

FIG. 6 shows an insulation arrangement.

FIG. 7 shows another insulation arrangement.

FIG. 8 shows a top view of an insulation arrangement.

DETAILED DESCRIPTION

FIG. 1 shows a semiconductor component on a weakly p-doped layer 1having a strongly p-doped layer 2 arranged on its rear side. A weaklydoped n-region 3 arranged on the front side of the component has astrongly p-doped anode region 4 embedded in it and is in turn surroundedby a buffer zone 5 having n-type doping to differentiate it from n-dopedlayer 3 and weakly p-doped layer 1. A p-channel 7 optionally introducedinto n-region 3 delineates a drift region 6 of n-region 3 from a regionin which p-wells 9, 10 are arranged. Details of p-wells 9, 10 are shownalong cross section 8 in FIG. 1a. A ring-shaped, strongly n-dopedcathode region 12 introduced into p-well 9 parallel to the edge of thep-well encircles a strongly p-doped region 11 at the center of p-well 9.Regions of p-well 9 between cathode region 12 and the edge of p-wells 9are referred to below as channel regions. Rounding of the corners of thechannel regions which occurs due to outward diffusion in the productionof the p-wells has not been shown here for the sake of simplicity.Optionally p-wells 9 facing away from anode region 4 and p-channel 7 arejoined by a p-doped web 13 introduced into n-region 3 when anarrangement of gate electrodes is applied as shown in FIG. 4. With anarrangement of gate electrodes according to FIG. 2, there is noconnection of p-wells 9 over such a p-web 13. The perspective viewaccording to FIG. 1 can be continued to the right and left in mirrorimage, so that a parallel connection of multiple anode regions can beimplemented, with more than one channel region being assigned to eachanode region. This semiconductor component designed as alateral-vertical-insulated gate bipolar transistor (LVIGBT) ismetallized on its rear side which is strongly p-doped (region 2) and isat a reference potential (ground), as are cathode regions 12 andstrongly p-doped regions 11 which are also connected to the referencepotential by a metallization applied over these regions. FIG. 1 does notshow this metallization. Metallization of strongly p-doped anode region4, which is at a positive potential in forward operation, is not shownfor the sake of simplicity. FIG. 2 shows the arrangement of gateelectrode 15 of the semiconductor component, without showing theinsulation layer between gate electrode 15 and the semiconductor body.Gate electrode 15, preferably made of polysilicon, covers n-region 3 andparts of p-wells 9. Gate electrode 15 completely covers channel regions14 which partially overlap strongly n-doped cathode regions 12. Thisforms an electrode surface with recesses whose contours are adapted tothe contours of the p-well or the n-cathode regions 12 arranged therein.Gate electrode 15 covers n-region 3 up to p-channel 7. P-channel 7 ispartially overlapped and is covered by a field plate which iselectrically connected to gate electrode 15 and is mounted at a greaterdistance from the semiconductor body than gate electrode 15. The fieldplate also covers parts of drift region 6 of n-region 3.

At a positive gate potential, inversion channels through which electronsenter drift region 6 are generated in channel region 14 of p-wells 9,10. Then the anode region injects holes into the drift region so that alateral current flow is established between the anode and cathode; atthe same time a vertical current flow is established between the anoderegion and the rear side of the semiconductor component. P-channel 7reduces field peaks at the edges of gate electrode 15.

FIGS. 3a-d show four embodiments of p-wells 9 and 10. FIG. 3a shows anarrangement of a p-well 9 having a closed ring-shaped cathode region 12completely encircling a strongly p-doped region 11. FIG. 3b shows ap-well arrangement 9 according to an exemplary embodiment of the presentinvention of p-wells that are not arranged in immediate proximity toanode region 4. The p-well has multiple cathode regions separated fromone another, labeled in their entirety with 20 as a cornerless cathoderegion. The arrangement according to FIG. 3b is derived from the idea ofthe arrangement according to FIG. 3a by removing strongly n-dopedregions at locations 23. The border between p-well 9 and stronglyp-doped region 11 introduced into the former can be seen atinterruptions 23. FIG. 3c shows a p-well arrangement 10 according to anexemplary embodiment of the present invention for p-wells in immediateproximity to anode region 4. P-well 10 here has a U-shaped cathoderegion 12, which can be seen in FIG. 3a by omitting n-doped regions atlocation 23 where the border between strongly p-doped region 11 andp-well 10 can be seen again by analogy with FIG. 3b. Interruption 23 isoriented toward anode region 4. FIG. 3d shows another embodiment of ap-well region 10 in immediate proximity to anode region 4. CornerlessU-shaped cathode region 22 has multiple partial regions havinginterruptions 23 in the corners of p-well 10 and on the side facinganode region 4 where the border between strongly p-doped region 11 andp-well region 10 can be seen in the view illustrated here.

A latch-up in the semiconductor component described here is triggered byforward polarization of the n+/p+ junction between strongly p-dopedregion 11 and strongly n-doped region 12 in p-wells 9 and/or 10 as aresult of current linkage of cathode region 12 through a hole current.To weaken this unwanted effect, p-well 10 does not have any region withstrong n-doping on its edge adjacent to the drift region in theembodiment of p-wells according to an exemplary embodiment of thepresent invention (FIG. 3c or 3 d). This yields a bypass for the holecurrent and increases the latch-up strength of the IGBT, because thereis no strongly n-doped region which could lead to early latch-upprecisely on the side with the highest hole current density. Because oftheir greater distance from drift region 6, a bypass at the edges can beomitted with the p-wells. Because of the geometry, however, there canalso be high hole current densities in the corners of p-wells 9. Thiseffect can be counteracted by two measures: first, by a mutually offsetarrangement of the p-wells resembling a chessboard pattern, but also byhole bypasses in the corners of p-wells 9 and 10 (see FIGS. 3b and 3 d).The latch-up strength is also increased by dividing the hole currentamong multiple p-wells and by the vertical current flow in the LVIGBT,especially in the case of a shutdown. The plurality ofparallel-connected channel regions obtained due to the island structureand the ring-shaped arrangement of cathode region 12 guarantees goodlet-through current characteristics at the same time. The let-throughcurrent characteristic is good because the quotient of the circumferenceand the area of p-wells 9 and 10 is large, and also a plurality ofislands can be arranged per anode region 4. The large value of thisquotient is an expression of a good conductivity modulation in the areaof the MOS control heads formed by the p-wells at a given channelresistance. The total channel resistance itself is low because aplurality of channel regions are connected in parallel. As alreadydescribed in conjunction with FIG. 1, p-wells 9, 10 are connected to oneanother and to the reference potential by cathode metallization. Thecontacting is designed so that strongly p-doped regions 11 and cathoderegions 12 are short-circuited together.

FIGS. 3e-f show modifications of the embodiment according to FIG. 3b:n-regions 20 are slightly extended so they come into contact at thecorners (FIG. 3e) or overlap slightly, forming a single cohesiven-region 20 (FIG. 3f); in the latter case, the interruptions havedegenerated to recesses at the corners. FIGS. 3g-l show modifications ofthe embodiments according to FIGS. 3b, e and f, where p-well 9 hasrounded or beveled corners associated with openings correspondinglybeveled or rounded at the corners in gate electrode 15 or 26 above it. Ahigher breakdown voltage in comparison with an arrangement according toFIGS. 3a, b, e and f is advantageous here. FIGS. 3m-t show modificationsof the arrangement according to FIG. 3d, by analogy with FIGS. 3e-l, allof which are modifications of the arrangement according to FIG. 3b. Withboth trough types 9 and 10, the corners of strongly p-doped regions 11located in the middle may also be rounded or beveled (FIGS. 3u, v and z,za) or pulled through to the edge of the openings in gate electrodes 15and 26 which define the shape of p-wells 9, 10 (FIGS. 3w, x, y and zb,zc, zd). It is advantageous here for region 11 to pull through on theentire side facing anode 4 in troughs 10 as far as the edge of theopenings of the gate electrodes. To simplify the diagrams, only p-wells9 and 10 and p-region 11 are shown in FIGS. 3u-zd.

FIG. 4 shows a LVIGBT component like that described in conjunction withFIG. 1, including p-web 13. In the manner already described inconjunction with FIG. 1, channel regions, in particular channel regionsadjacent to anode region 4, can be controlled by a control gate 26,whereas channel regions more remote from drift region 6 and anode region4 can be controlled by a clamp gate 27 electrically insulated fromcontrol gate 26.

LIGBT components having multiple parallel-connected channel regions peranode region permit a separation of gate control into a control gate anda clamp gate in general, where the MOS channel regions assigned to thegates each control the same anode region. Such a division can be usedwith strip-shaped p-wells, such as those described in German PublishedPatent Application 197 25 091, for example. The use of such a divisionin an electronic circuit is described in greater detail in conjunctionwith FIGS. 5a to 5 c.

FIGS 5 a to 5 c illustrate various embodiments of how a field-controlledsemiconductor component having a separate control gate and clamp gateare tied into an electronic circuit. FIG. 5a shows an LIGBT 30 having ananode terminal A and a cathode terminal K plus a rear side terminal RS.The cathode terminal and rear side terminal are connected to ground.Anode terminal A is connected to a power supply voltage U by aninductive load 31. Component 30 is controlled over control gate 26 by acontrol circuit 36 designed as a resistor at whose input 38 a controlsignal can be applied. A clamp circuit 35 composed of a seriesconnection of two Zener diodes and one diode and another resistorconnects anode terminal A of the component to clamp gate 27. In FIG. 5b,control circuit 36 is fused with clamp circuit 35 to form a unit. Acorresponding potential is applied to control gate 26 and clamp gate 27over the control signal applied to control input 38 and the anodepotential according to circuit 35, 36. FIG. 5c shows a generalizeddiagram of the control of control gate 26 and clamp gate 27 of LIGBT 30,where a clamp circuit 35 connected to anode terminal A is provided, itsoutput signal is applied to control circuit 39 which processes thecontrol signal applied to control input 38 together with the outputsignal of clamp circuit 35, applying suitable potentials to control gate26 and clamp gate 27. As described above, a latch-up is triggered by aforward polarity of the n+/p+ junction in the p-wells due to the currentlinkage of the cathode region through a hole current. At a highinductance of load 31, high voltage peaks may occur at anode terminal A.To reduce the voltage peak rapidly without triggering a latch-up, thegroup of channel regions farther away from drift region 6 and/or anoderegion 4 may be controlled over clamp circuit 35 and clamp gate 27. Thisprevents a high hole current density in the p-wells close to the driftregion and thus suppresses premature latch-up. On the other hand, thesenearby p-wells 10 draw off some of the hole current, thus relieving theload on p-wells 9 remote from the drift region so that these p-wellscarry most of the current in the case of voltage peaks at anode terminalA because of the greater control in comparison with the p-wellscontrolled over the control gate. FIG. 5a shows a complete separation ofthe clamp circuit and the control circuit in contrast with theembodiment according to FIG. 5b. FIG. 5c shows in a more general form apartial separation of the clamp circuit and control circuit with theadvantage that it relieves the load on the control circuit, because thesteep-edged signals occurring in the clamp circuit can be kept away fromthe control circuit. The latch-up strength is also increased by thevertical current flow occurring in the LVIGBT in particular in ashutdown case and in a clamp case. This current component flowing fromthe anode region to the rear side leads to relief of the load on thelateral current path for a given anode current density and is especiallyhigh in a shutdown case and in a clamp case.

FIG. 6 shows a detail 49 of a semiconductor chip having a region 40 inwhich is arranged an LIGBT of the type described previously. This LIGBTis shown only schematically, especially in the area of p-well 9. Inaddition, this also shows a rear side contact RS connected to ground 46and applied to the rear side of semiconductor chip 49 in addition togate electrode G and anode terminal A applied to anode region 4. Weaklyp-doped region 1 has a layer thickness 45 of more than 10 μm in the areaof region 40. There is also a region 43 where additional LIGBTs or alogic circuit can be arranged. Additional n-region 48 may be designedthicker in comparison with n-region 3 of region 40 or it may have adifferent concentration of dopant. Therefore, n-region 3 is designed tobe relatively thin in region 40 only because a resurf arrangement leadsto another advantageous embodiment of the component according to anexemplary embodiment of the present invention in particular,as describedalready in German Published Patent Application 197 25 091. Region 43 isseparated from region 40 by an insulation arrangement 41. Thisinsulation arrangement 41 has a strongly p-doped wall 47, completelypermeating weakly n-doped region 48 as well as weakly n-doped region 3and electrically connected to weakly p-doped region 1. P-wall 47 isshort-circuited with cathode terminal K and is connected to referencepotential 46 (ground). In FIG. 7, insulation arrangement 41 does nothave one closed p-wall 47 but instead has two partial walls 50, 51laterally enclosing a weakly n-doped region 52. This laterally enclosedn-region 52 receives a positive protection potential V. Insulationarrangement 41 in FIGS. 6 and 7 encloses at the edges the LIGBT which isarranged in region 40. In FIG. 7, region 40 is also shielded by p-wall50 only toward region 43. N-region 52 is completely surrounded laterallyby p-walls 50 and 51; regions 50 and 51 are connected by additionalstrongly p-doped regions in front of and behind the plane of the drawingin FIG. 7 (not shown), so that n-region 52 is completely encircledlaterally by strongly p-doped regions.

Insulation arrangements 41 according to FIGS. 6 and 7 are suitable inparticular for conductivity-modulated power components such as LIGBTswith a high blocking ability and use the layer sequence of weaklyp-doped substrate 1 on strongly p-doped region 2 which is compatiblewith the LIGBT. The strongly p-doped walls introduced from the top ofthe chip, like strongly p-doped layer 2 arranged on the rear side of thechip, draw off holes which assume a portion of the current transportwithin the chip, in particular in the LIGBT. To minimize the on-statevoltage drop of the LIGBT, insulation arrangement 41 can be used only atthe periphery of the output stage(s). At the edge of the chip, theinsulation arrangement also at the same time fulfils the function of adefined edge closure. Furthermore, an intermediate region 52 which isalso provided, as shown in FIG. 7, may receive a positive potential Vand may be used to draw off part of the electrons carrying part of thetotal current. Strongly p-doped region 2 on the rear side of the chipalso draws holes off to deep walls 47, 51, 50 and thus, together withthem, connects the insulation region well to ground. Deep n-region 52shown in FIG. 7, which is connected to positive voltage V by a strongn-doping zone 54, also draws off electrons. A lateral current flow andthus a transverse influence on regions 40 and 43 are effectivelyshielded. Insulation arrangements 41 are compatible with buried layersfor insulation in the area of logic circuits arranged in regions 43.These insulation arrangements can also be used with semiconductorcomponents which have, instead of island structures, intermeshed fingerstructures for the anode and cathode, as described in German PublishedPatent Application 197 25 091, for example.

FIG. 8 shows as an example a top view of a semiconductor arrangementhaving two LVIGBT regions 40 between which are arranged two logicregions 43. The edge of the arrangement and regions 40 are surrounded bypartial wall 51, while logic regions 43 are also separated from theLVIGBT regions by another partial wall 50. Intermediate region 52 whichwas already described above and receives a protection potential islocated between partial walls 50 and 51. The contacts of the partialwalls not shown in FIG. 8 are connected to a common ground point so thatfirst regions 50 and 51 are electrically connected and then finally thecommon contacts of regions 50 and 51 are joined. The common ground pointmay be arranged inside or outside the chip. In the latter case, thecontacts of regions 50 and 51 are carried over wire bonds to legs of thehousing of the integrated arrangement and then are connected externally.Crosstalk between LVIGBT regions or between the LVIGBT regions and logicregions 43 is minimized by such separate ground leads. Such crosstalkdevelops due to voltage drops at the ground metallization when a highcurrent is carried over it in operation. The different grounds shouldtherefore be joined more or less in a star shape only at a common point.

What is claimed is:
 1. A field-controlled semiconductor component foruse as a lateral-insulated gate bipolar transistor, the componentcomprising: a p-layer; an n-region having at least one p-well and ananode region, the n-region being arranged on a front side of the p-layerand the at least one p-well having a channel region controllable by agate electrode; and at least one strongly n-doped cathode region beingembedded in the at least one p-well, wherein: the at least one stronglyn-doped cathode region is in a ring shape and runs parallel to an edgeof the at least one p-well, the at least one strongly n-doped cathoderegion has at least one of an interruption and a recess in at least onelocation, and the at least one strongly n-doped cathode region of the atleast one p-well adjacent to the anode region has an interruption alongan entire side facing the anode region.
 2. The component of claim 1,wherein: one of the at least one p-well is at least one of rectangularand square in shape; and the at least one of an interruption and arecess in the cathode region is arranged at at least one corner.
 3. Thecomponent of claim 1, including a p-channel embedded in the n-regionbetween the at least one p-well and the anode region.
 4. The componentof claim 1, including: a first group of channel regions controllable bya clamp gate; and a second group of channel regions controllable by acontrol gate electrically insulated from the clamp gate.
 5. Thecomponent of claim 4, further comprising: an external inductive loadcoupled in series; a control circuit having a control input forreceiving a control signal; and a clamp circuit coupled to an anodeterminal; wherein at least one of the clamp gate and the control gate iscontrollable as a function of an anode potential and the control signalby using at least one of the clamp circuit and the control circuit. 6.The component of claim 1, further comprising: an insulation arrangement,wherein: the at least one p-well and the anode region are completelysurrounded laterally by the insulation arrangement; and the insulationarrangement having a strongly p-doped wall completely enclosing theanode region, permeating surrounding n-regions, being coupled to thep-layer and being short-circuited with the at least one strongly n-dopedcathode region, the strongly p-doped wall having two partial walls insections for enclosing an intermediate region receiving a positiveprotection potential.
 7. A field-controlled semiconductor component foruse as a lateral-insulated gate bipolar transistor, the componentcomprising: a p-layer; an n-region having at least one p-well and ananode region, the n-region being arranged on a front side of the p-layerand the at least one p-well having a channel region controllable by agate electrode; and at least one strongly n-doped cathode region beingembedded in the at least one p-well, wherein: the at least one stronglyn-doped cathode region is in a ring shape and runs parallel to an edgeof the at least one p-well, the at least one strongly n-doped cathoderegion has at least one of an interruption and a recess in at least onelocation, and the at least one strongly n-doped cathode region of the atleast one p-well adjacent to the anode region has an interruption alongan entire side facing the anode region; wherein: the n-region has astrongly p-doped wall permeating surrounding n-regions, being coupled tothe p-layer and being short-circuited with the at least one stronglyn-doped cathode region, the strongly p-doped wall being part of aninsulation arrangement completely laterally surrounding the at least onep-well and the anode region; and the p-layer is covered on a sideopposite the n-region by a strongly p-doped region so that at least partof the strongly p-doped region functions as a part of the insulationarrangement so that holes for electrically insulating a regionsurrounding the insulation arrangement are drawable off by the stronglyp-doped wall and also over the strongly p-doped region.
 8. The componentof claim 7, wherein the strongly p-doped wall has two partial walls insections for enclosing an intermediate region receiving a positiveprotection potential.
 9. The component of claim 7, wherein: n-dopingsand p-dopings of the component are exhanged; and all potentialsdeviating from a ground reference potential have an opposite polarity.10. A field-controlled semiconductor component comprising: a p-layer; ann-region having at least one p-well and an anode region, the n-regionbeing arranged on a front side of the p-layer and the at least onep-well having a channel region controllable by a gate electrode; and ann-doped cathode region being embedded in the at least one p-well,wherein: the n-doped cathode region is in a ring shape and runs parallelto an edge of the at least one p-well, the n-doped cathode region has atleast one of an interruption and a recess in at least one location, andthe n-doped cathode region of the at least one p-well adjacent to theanode region has an interruption along a side facing the anode region.11. The component of claim 1, wherein: n-dopings and p-dopings of thecomponent are exchanged; and all potentials deviating from a groundreference potential have an opposite polarity.
 12. The component ofclaim 10, wherein: n-dopings and p-dopings of the component areexchanged; and all potentials deviating from a ground referencepotential have an opposite polarity.
 13. The component of claim 1,including a p-channel embedded in the n-region between the at least onep-well and the anode region; wherein: one of the at least one p-well isat least one of rectangular and square in shape; and the at least one ofan interruption and a recess in the cathode region is arranged at atleast one corner.
 14. The component of claim 13, including: a firstgroup of channel regions controllable by a clamp gate; and a secondgroup of channel regions controllable by a control gate electricallyinsulated from the clamp gate.
 15. The component of claim 14, furthercomprising: an external inductive load coupled in series; a controlcircuit having a control input for receiving a control signal; and aclamp circuit coupled to an anode terminal; wherein at least one of theclamp gate and the control gate is controllable as a function of ananode potential and the control signal by using at least one of theclamp circuit and the control circuit.
 16. The component of claim 1,wherein the gate electrode is made of polysilicon.
 17. The component ofclaim 1, wherein the lateral-insulated gate bipolar transistor is alateral-vertical-insulated gate bipolar transistor.